The present invention relates to an emitter-coupled logic circuit device, and especially to an emitter-coupled logic circuit device with low power consumption.
When high-speed signal processing is required, an emitter-coupled logic (ECL) circuit device is generally used.
When an ECL device is formed as a large-scaled integrated circuit (LSI), it is often required that its external characteristics, for example, input and output level and the voltage source level, be made equivalent to those of a commercial ECL IC (e.g., ECL 10 K series by Motorola corp.).
A prior art ECL LSI is illustrated in FIG. 1. The ECL LSI of FIG. 1 comprises an input buffer circuit 1', inner logic gate circuits 21' . . . 2n', and an output buffer circuit 3'. The power consumption of the ECL LSI of FIG. 1, however, is increased for the following reasons:
1. Even though the inner circuits of the ECL LSI can be operated by a low voltage source (e.g., -2.0 V), the ECL LSI must be driven by a high voltage source, for example -5.2 V or -4.5 V, in order to match with the commercial ECL IC. PA1 2. Since each output of the ECL is connected through a load resistance of 50 .OMEGA. to a voltage source of -2.0 V, a current of about 23 mA flows out from one output terminal when it is at the "H" level (standardly -0.85 V). In order to maintain the "H" level of the output terminal above the prescribed voltage even when the above-mentioned current flows, it is necessary to make the ouput impedance of the ECL circuit sufficiently low. Thus, the main current path of the output buffer circuit which forms the output portion of the device cannot use elements having an impedance higher than a certain value. Accordingly, the current flowing inside of the output buffer circuit cannot decrease below a predetermined value regardless of the LSI manufacture technology or the target value of the switching speed.
The above factors have tended to result in a larger power consumption of ECL LSI's. However the power consumption allowed for one LSI chip is limited by the cooling ability of the chip arrangement. Therefore, there has been a tendency of having to reduce the integration scale of ECL LSI's to keep down the increase in power consumption.